The Mealy Machine

A Comprehensive, Elite Guide to Input-Driven Finite State Transducers

1. Definition & Fundamental Concepts

In the Theory of Computation, a Mealy Machine is a finite-state machine whose output values are determined by both its current state AND the current input. This makes it fundamentally different from a Moore machine, where output is tied solely to the state.

Because the output is generated during the transition between states, Mealy machines react instantly to inputs. They generally require fewer states than Moore machines to perform the same task.

Formal Mathematical Definition

A Mealy Machine is formally defined as a 6-tuple (Q, Σ, Δ, δ, λ, q₀) where:

Q : A finite set of states.
Σ (Sigma) : A finite set of input symbols.
Δ (Delta) : A finite set of output symbols.
δ (delta) : The transition function mapping Q × Σ → Q.
λ (lambda) : The output function mapping transitions to outputs Q × Σ → Δ.
q₀ : The initial (start) state.

CRITICAL RULE: Synchronous Output
Unlike Moore machines, Mealy machines do NOT output an extra character at the start. The length of the output string is exactly equal to the length of the input string. For an input of length N, the output is length N. Also, just like Moore machines, Mealy machines have NO final/accepting states.

2. Expert Tips & Tricks for Designing Mealy Machines

Designing Mealy machines is highly efficient once you grasp that the transition arrow does all the heavy lifting.

Edge Notation: Every transition arrow must be labeled as Input / Output. E.g., 1 / 0 means "When reading input 1, output 0 and take this path."
State Design: The states in a Mealy machine merely represent "what we have seen so far" (memory). The state circle ONLY contains the state name (e.g., q0), not the output.
Immediate Reaction: If you are designing a sequence detector (e.g., detecting "101"), the output of '1' happens on the final transition that completes the sequence, not by entering a final state.
Fewer States: To detect a sequence of length N, a Mealy machine typically needs exactly N states (compared to N+1 for Moore).

3. Complete Masterclass Examples (1 to 10)

Below are meticulously engineered step-by-step designs of Mealy Machines. Notice how the outputs live exclusively on the transition arrows.

Example 1: 1's Complement Generator

Problem: Design a Mealy machine that takes a binary input string and produces its 1's complement (flips 0s to 1s and 1s to 0s).

Logic & State Definition: A Mealy machine can do this in a single state! Since the output only depends on the current input (flip whatever comes in) and we don't need to "remember" anything about past inputs, 1 state is sufficient.

q0: Base state. If input is 0, output 1. If input is 1, output 0.

Example 2: 2's Complement Generator (LSB to MSB)

Problem: Generate the 2's complement of a binary string read from Least Significant Bit to Most Significant Bit.

Logic & State Definition: Rule: Pass all '0's as '0's until the first '1' is seen. Pass that first '1' as '1'. Afterward, flip every subsequent bit.

q_wait: Waiting for first '1'. Read 0 -> Out 0. Read 1 -> Out 1 (and go to flip state).
q_flip: Flip mode. Read 0 -> Out 1. Read 1 -> Out 0.

Example 3: Sequence Detector "10" (Overlapping Allowed)

Problem: Output 1 whenever the exact sequence "10" is completed. Output 0 otherwise.

Logic & State Definition: Sequence length is 2, so Mealy needs 2 states.

q0: Start / Haven't seen '1'.
q1: Just saw '1'. If we see '0' now, the sequence is complete! Transition to `q0` and output `1`.

Example 4: Sequence Detector "101" (Overlapping Allowed)

Problem: Output 1 when "101" is completed, else 0.

Logic & State Definition: Sequence length is 3, requires 3 states.

q0: Start state.
q1: Saw '1'.
q2: Saw '10'. If we see '1' from here, sequence is met! Go to `q1` (since this '1' could start a new "101") and output `1`.

Example 5: Residue Modulo 3 (Binary Input)

Problem: Output the remainder when the binary string read so far is divided by 3.

Logic & State Definition: Formula: Next_Mod = (Current_Mod * 2 + input) % 3. Output equals the destination state's mod value.

q0: Current mod 0.
q1: Current mod 1.
q2: Current mod 2.

Example 6: Toggle Flip-Flop (T-Flip Flop)

Problem: Over Σ={0,1}, act as a T-Flip Flop. Input '1' toggles the output state, Input '0' maintains it. Initial output state is 0.

Logic & State Definition:

q0: Represents output state 0.
q1: Represents output state 1.

Example 7: End Character Identifier

Problem: Over {a,b}, output A if the string ends in "aa", B if it ends in "bb", and C otherwise.

Logic & State Definition:

q0: Start state (Neither).
qa: Last char was 'a'. If 'a' read -> output A. If 'b' read -> output C.
qb: Last char was 'b'. If 'b' read -> output B. If 'a' read -> output C.

Example 8: Even Parity Generator

Problem: For each binary input bit, output a bit such that the total number of 1s in the entire system (input + output combined so far) is Even.

Logic & State Definition:

qE: Received Even number of 1s. If '1' is received -> becomes Odd -> Output 1 to make it Even again.
qO: Received Odd number of 1s. If '0' is received -> remains Odd -> Output 1 to make it Even.

Example 9: Binary Incrementer (Add 1)

Problem: Add 1 to a binary number read from LSB to MSB. E.g., 101 (read backwards) -> 011.

Logic & State Definition: When adding 1 to the LSB, there is an initial Carry of 1.

q_carry_1: Start state. Add 1 to input. Input 0 -> Out 1, Carry becomes 0. Input 1 -> Out 0, Carry remains 1.
q_carry_0: No carry. Pass inputs unchanged (0/0, 1/1).

Example 10: Consecutive Identical Symbols Detector

Problem: Output 1 if the current symbol matches the immediately preceding symbol (e.g., "00" or "11"). Output 0 otherwise.

Logic & State Definition:

qS: Start state. Output 0 for any first symbol.
q0: Last symbol was '0'. Read 0 -> Out 1. Read 1 -> Out 0.
q1: Last symbol was '1'. Read 1 -> Out 1. Read 0 -> Out 0.

Example 11: Sequence Detector "010" (Overlapping)

Problem: Output 1 whenever the sequence "010" is completed in the input stream. Overlapping is allowed.

Logic & State Definition: Requires exactly 3 states (Length of sequence).

q0: Start state.
q1: Saw '0'.
q2: Saw '01'. If '0' is read next -> Match! Output 1. The new string ends in '0', so transition back to `q1`.

Example 12: Sequence Detector "aba" (Overlapping)

Problem: Output 1 when "aba" is completed. Alphabet {a, b}.

Logic & State Definition:

q0: Start state.
qa: Saw 'a'.
qab: Saw 'ab'. If 'a' is read -> Match! Output 1 and transition to `qa` (overlapping 'a').

Example 13: Count Parity of '1's Generator

Problem: Output E if the total number of '1's read so far is Even, and O if it is Odd. Alphabet {0,1}.

Logic & State Definition:

qE: Currently Even. Read 0 -> Out E. Read 1 -> Out O (and transition to qO).
qO: Currently Odd. Read 0 -> Out O. Read 1 -> Out E (and transition to qE).

Example 14: Count 'a's Modulo 3

Problem: Output the remainder of the number of 'a's read so far divided by 3. Alphabet {a, b}.

Logic & State Definition:

q0: Mod 0. Read 'b' -> Out 0. Read 'a' -> Out 1 (transition to q1).
q1: Mod 1. Read 'b' -> Out 1. Read 'a' -> Out 2 (transition to q2).
q2: Mod 2. Read 'b' -> Out 2. Read 'a' -> Out 0 (transition to q0).

Example 15: Sequence Detector "1011"

Problem: Output 1 when "1011" is completely detected. Overlapping allowed.

Logic & State Definition: Length 4 sequence requires exactly 4 states in Mealy.

q0: Start.
q1: Saw '1'.
q2: Saw '10'.
q3: Saw '101'. Read '1' -> Output 1 (Match!). Next state `q1` because the '1' can overlap.

Example 16: "Matches First Bit" Detector

Problem: Output 1 if the current bit matches the very first bit of the string. Output 0 otherwise.

Logic & State Definition:

qS: Start. Records first bit. If 0 -> Out 1, go to q0. If 1 -> Out 1, go to q1.
q0: First bit was 0. Read 0 -> 1. Read 1 -> 0.
q1: First bit was 1. Read 1 -> 1. Read 0 -> 0.

Example 17: D-Flip Flop (Delay Element)

Problem: Output the exact bit that was received in the previous clock cycle. For the very first input, output 0.

Logic & State Definition: Because a Mealy machine outputs synchronously, reading the first bit (e.g., '1') from the start state transitions to the "saw 1" state while outputting the default '0'.

q0: Previous bit was 0 (also the Start State). Input 0 -> Out 0. Input 1 -> Out 0 (transition to q1).
q1: Previous bit was 1. Input 1 -> Out 1. Input 0 -> Out 1 (transition to q0).

Example 18: Ends in "ab" or "ba"

Problem: Output 1 if the last two characters read are "ab" or "ba" (Alternating ends). Output 0 otherwise.

Logic & State Definition:

qS: Start state.
qa: Last char 'a'. Read 'b' -> Out 1 (transition to qb). Read 'a' -> Out 0.
qb: Last char 'b'. Read 'a' -> Out 1 (transition to qa). Read 'b' -> Out 0.

Example 19: Rising Edge Detector (0 to 1)

Problem: Output 1 exactly once when the input transitions from 0 to 1. Output 0 at all other times.

Logic & State Definition: Assume initial state represents a default '0' level.

q0: Currently reading 0s. Read 0 -> Out 0. Read 1 -> Out 1 (Rising Edge! transition to q1).
q1: Currently reading 1s. Read 1 -> Out 0. Read 0 -> Out 0 (Falling Edge, transition back to q0).

Example 20: Sink State ("111" Trigger)

Problem: Output 1 only after the string "111" has been encountered. Once "111" is seen, output 1 for all subsequent inputs indefinitely.

Logic & State Definition:

q0: Start / Reset on 0. Read 0 -> Out 0. Read 1 -> Out 0 (goto q1).
q1: Saw one 1. Read 0 -> Out 0. Read 1 -> Out 0 (goto q2).
q2: Saw two 1s. Read 0 -> Out 0. Read 1 -> Out 1 (Match! goto q3).
q3: Sink State. Read 0 or 1 -> Out 1.